(1) Field of the Invention
The invention relates to clock signal generation. More specifically, the invention relates to generation of transmit and receive clocks to satisfy Universal Serial Bus (USB) requirements.
(2) Related Art
The Universal Serial Bus (USB) is a high-speed serial bus following a protocol defined in Universal Serial Bus Specification, Version 1.0 (USB Spec). Modification of this specification can be expected from time to time. However, the USB spec provides a standardized approach for peripheral interconnection with a host computer. The USB is set up in a tiered topology with a host on the top tier and USB hubs and functions on subsequent tiers. Each USB device, whether it be a hub, the host, or a function, has associated therewith a serial interface engine (SIE) which provides an interface between the hub, host, or function and the transceiver which transmits or receives signals across the serial line. Generally, the SIE takes care of all the USB low level protocol matters such as bit stuffing, cyclic redundancy checks (CRCs), token generation, and hand-shaking.
To accomplish these required tasks, the SIE must generate a transmit clock SIGNAL and a receive clock signal. The transmit clock has a uniform duty cycle and operates at 12 MHz at full speed or 1.5 MHz for slow speed devices. The receive clock duty cycle may be stretched or shrunk, depending on data jitter present on the USB. The requirements for accommodating data jitter are discussed in the USB Spec, Section 7.1.13. Prior art techniques have typically employed two different sources to generate the transmit and receive clocks. A multiplexer is then employed to select between the transmit clock and the receive clock, depending on whether the interface is in a transmit mode or receive mode.
FIG. 1 shows an example of a prior art transmit and receive clock generator. In the figure, states are numbered with the hexadecimal value of their binary equivalents, and bracketed numbers correspond to the clock value supplied to a multiplexer 18 by a transmit state machine 16 and a receive state machine 17. The transmit clock is generated by a free-running state machine 16 responsive to an externally generated 48 megahertz clock (or 4x clock) at full speed (6 MHz for slow speed devices), the state machine having four states, 0 through 3, with the output clock being "0" in states 0 and 1, and "1" in states 2 and 3. Thus, this state machine effectively implements a divide by four to divide the 4x clock to generate a 1x transmit clock at the bit rate of the device. An externally generated reset signal 19 forces the state machine 16 into state 0.
A four bit digital phase lock loop (DPLL) state machine 17 is used to generate the receive clock. The DPLL state machine 17 is also clocked by the 4x clock. One of ordinary skill in the art will recognize how this four bit state machine satisfies the jitter requirements of the USB Spec by expanding or shrinking the duty cycle of the receive clock responsive to signals on the data line. If the data stream is perfect, the DPLL will follow the path 5.fwdarw.7.fwdarw.6.fwdarw.4.fwdarw.1.fwdarw.3.fwdarw.2.fwdarw.0.fwdarw.5. As the states are assigned, the received data can be derived by watching the second most significant bit of the state designations. The DPLL will continue cycling until a transmit indicator or an end of packet receive (EOPR) signal forces the DPLL back to an idle state (state C). The reset signal 19 always forces the receive state machine 17 into state C.
Because only one clock signal can be applied to the rest of the serial interface, in any mode, the transmit state machine 16 and the receive state machine 17 are coupled through the multiplexer 18 so that a single 1x clock signal is supplied to the rest of the serial interface engine and the device. The multiplexor 18 adds delay in the clock path. Additionally, synthesis of the multiplexer 18 is quite difficult and requires great effort to ensure operability at all operating conditions. Switching between the transmit clock and the receive clock often causes a glitch in the signal which can cause the SIE to malfunction. To avoid this glitch-precipitated malfunction, the multiplexer 18 must be custom-designed to insure that neither clock will toggle while switching is occurring. Such customization is both design intensive and inflexible, requiring redesigns for each new version of an underlying product.
In view of the foregoing, it would be desirable to be able to generate the receive and transmit clock signals having increased flexibility and reduced design effort and cost without decreasing functionality over that which exists today and without deviating from the USB Spec.